1. Field of the Invention
The invention relates to integrated circuit processing and, more particularly, to the patterning of interconnection lines on an integrated circuit.
2. Description of Related Art
Modern integrated circuits use conductive interconnections to connect the individual devices on a chip or to send and receive signals external to the chip. Popular types of interconnections include aluminum alloy interconnection lines and copper interconnection lines coupled to individual devices, including other interconnection lines, by interconnections through vias.
A typical method of forming an interconnection is a damascene process that involves forming a via and an overlying trench in a dielectric to an underlying circuit device, such as a transistor or an interconnection line. The via and trench are then lined with a barrier layer of a refractory material. Common refractory materials include titanium nitride (TiN) or tantalum (Ta). The barrier layer serves, in one aspect, to inhibit the diffusion of the interconnection material that will subsequently be formed in the via into the dielectric. Next, a suitable seed material is deposited on the wall or walls and base of the via. Suitable seed materials for the deposition of copper interconnection material include copper and nickel. Next, interconnection material, such as copper, is deposited in a sufficient amount to fill the via and trench using, for example, an electroplating process. Thus, the interconnection formed in the via includes the barrier layer material since barrier layer material lines the base of the via.
A second method for forming an interconnection is described in the U.S. patent application Ser. No. 09/001,349, filed Dec. 31, 1997, assigned to Intel Corporation of Santa Clara, Calif., and titled “A Single Step Electroplating Process for Interconnect Via Fill and Metal Line Patterning.” That method includes forming a via in a dielectric to an underlying circuit device, such as a transistor or an interconnection line. The via and a top surface of the dielectric are then lined and covered with a barrier layer and a suitable seed material, respectively. A layer of photoresist or other masking material is then patterned over the seed material covering the top of the dielectric. An electroplating process is used to deposit a conductive material such as copper to fill the via and form an interconnection line over the dielectric according to the patterned masking material. The masking material and underlying conductive material is then removed. Once again, the interconnection formed in the via generally includes the barrier layer since barrier layer material lines the base of the via.
In general, the resistivity of the barrier layer material is much greater than the resistivity of copper. Thus, the inclusion of the barrier layer material at the base of the via and as part of the interconnection increases the resistivity of the interconnection. What is needed is an interconnection having reduced resistivity and a method of forming an interconnection with reduced resistivity compared to the prior art.